Computer systems utilize cache memories to enhance system performance. A data cache contains the cached data, and a cache tag memory contains a portion of the address field, usually the most significant bits, of the addresses of the data stored in the cache. A processor, when making a memory access, accesses the desired memory location through the cache. If the desired location is already in the cache, access is complete. If it is not, the memory location is fetched from main system memory and loaded into the cache.
Any device used in specialty designs such as cache memories must take special device functions into consideration. For example, cache memories must occasionally be cleared, or written to in a bulk write operation. Often times the cache tag memory contains a valid bit for each address location, which is cleared to invalidate each entry. One technique for clearing cache memories utilizes a bulk write operation, which clears the entire memory in the cache tag for all tag bits including the valid bits. This allows the entire memory to be reset in a single step.
Special functions such as bulk write operations must be properly handled by any device design. Designs which improve device speed often do so at the expense of being able to handle more complex functions. Devices which can perform more complex functions such as flash clear often must sacrifice speed in order to do so.
Conventional memory devices such as static random access memories (SRAMs) are generally arranged in rows and columns. In these memory devices, a row select line, generally decoded from a row address value, connects each of a number of memory cells associated with the row address value to a pair of associated bit lines; each pair of bit lines is associated with a column of memory cells.
In prior systems, to clear the memory, traditional methods would clear the entire memory upon power up of the system or invalidation upon switching between programs by storing a zero in all of the memory locations by various methods. One method requires sequentially addressing all of the memory locations and forcing a zero therein. Another method of clearing the entire memory requires selecting all word lines and then writing a selected logic state into all cells.
One disadvantage to forcing all memory cells to zero is that drivers must be present which can drive all of the memory locations to a "0" logic state. The drive requirements for switching capacitances of the word lines and bit lines, thus clearing all of the memory cells, results in relatively large drive transistors. The resulting peak current of these methods often exceeds acceptable limits. If the entire memory can be cleared, one section at a time, for example, the current transients can be minimized or staggered. This approach, however, requires additional time to clear the entire memory.
Another method for clearing memory cells requires unbalancing the memory cells by raising ground on one side of cross coupled inverters. This method has been typically used with full CMOS cells. A disadvantage of this type of selective clearing is that some type of interconnection is required for each of the memory cells which increases the amount of space occupied by the memory array. To clear the memory cells, each column of memory cells requires a separate run of conductive material to interface with each of the memory cells for the clear function.
It is not necessary, however, to clear the entire memory. Only valid bits in cache applications, for example, need to be cleared. With larger densities, it is desirable to confine clear, or bulk write, functions to only a portion of the memory to reduce transient current and time required to clear the memory. There, therefore, exists a need for a more versatile memory that allows clearing of less than all of the memory cells.
It would be desirable for the invention to provide a circuit in a semiconductor memory which isolates a selected group of memory cells for clearing. It would further be desirable to provide a means of isolating the selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. It would yet be desirable to bulk write to each memory cell in each column of the selected group of memory cells. Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.